Incorporating yield prediction into the design and layout of integrated circuit components allows more efficient design and production of integrated circuits. State-of-the-Art Critical Area Analysis (CAA) is typically used in performing yield estimations for an integrated circuit design. The ever increasing manufacturing costs associated with the ever decreasing component sizes in the deep-submicron semiconductor arena have increased the impact of effective yield prediction in improving the economy of efficient integrated circuit production.
The critical area of an integrated circuit design is the expected area of a chip that is lost to random substrate and/or circuit defects. Such random substrate and/or circuit defects on an integrated circuit die prevent the proper formation of, for example, a conductive trace of a circuit and thereby causes the failure of one or more integrated circuits formed on an integrated circuit die. A critical area reflects the sensitivity of a circuit design and layout to spot defects occurring during chip fabrication. Examples of spot defects are substrate and/or circuit defects caused by particles, such as dust and other contaminants. Spot defects in an integrated circuit component can lead to conductive trace shorts, opens, or problems related to blockage of inter-layer vias.
Spot defects analyzed by critical area analyses include inter-conductor short spot defects, intra-conductor open spot defects, defects causing blockages of inter-layer vias, and defects causing combination faults. An inter-conductor short spot defect is a spot defect that causes a conductive short between two conductors of a circuit. The susceptibility of a circuit to failure due to inter-conductor short spot defects varies inversely with inter-conductor spacing and varies in concert with the length of conductors that are close to one another since smaller defects will affect adjacent conductors that are closer to each other and conductors that are close to each other for longer lengths are more likely to encounter a spot defect.
Intra-conductor open spot defects are spot defects that create a non-conductive area on a circuit that can interfere with the creation of a conductive trace. The susceptibility of a circuit to failure due to intra-conductor open spot defects varies in concert with conductor length and varies inversely to conductor width. Longer conductors are more likely to encounter an intra-conductor open defect and wider conductors are more likely to be wider than an encountered defect and therefore still be conductive.
The calculation of a critical area for a particular integrated circuit design requires a definition of the detail metal shapes that are to be used in the integrated circuit. Critical area analysis is computationally expensive and time consuming. Therefore, critical area analysis is usually applied in the later or post-design stages for chip evaluation. However, designs are almost fixed in those late design stages and only simple local changes can be applied. Although local tuning can help to improve the layout, the compensation ability is strictly constrained by the existing design.
Therefore a need exists to overcome the problems with the prior art as discussed above.